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gennum corporation p.o. box 489, stn. a, burlington, ontario, canada l7r 3y3 tel. +1 (905) 632-2996 fax. +1 (905) 632-5946 e-mail: info@gennum.com www.gennum.com revision date: november 2000 document no. 522 - 34 - 00 preliminary data sheet gs1501 features ? smpte 292m compliant nrz(i) encoding smpte 292m scrambler with bypass option internal fifos for anc data insertion (1024 bytes on y and c channels) selectable trs insertion selectable line number insertion selectable line based crc insertion selectable active picture illegal code re-mapping 20 bit 3.3v cmos compatible input data bus optimized output interface to gs1522 single +3.3v power supply 5v tolerant i/o applications smpte 292m serial digital interfaces. description the gs1501 hdtv serial digital formatter formats the hdtv luma and chroma data according to smpte 292m prior to serialization by the gs1522 hdtv serializer. the gs1501 optionally inserts trs and line number signals based on externally supplied h, v and f signals. the device also allows the insertion of crcs based on trs signals embedded in the input data streams, should the user choose not to supply external hvf signals. following the insertion of trs, line number, and crc, protected words of 000-003 and 3fc to 3ff occurring during the active video period are optionally re-mapped to 004 and 3fb respectively. in addition, anc data may be inserted into the video stream through an internal fifo interface. prior to exiting the device smpte 292m compliant nrz(i) encoding and scrambling may be performed on the data stream. block diagram ordering information part number package temperature GS1501-CQR 128 pin mqfp 0c to 70c input buffer and blanker trs and line number detection pclk_in data _ o u t [19:0] [h:v:f] bp_sc illegal code remapping code protect anc_in[9:0] ff_sta [2:0] trs_ins ln_ins crc_ins nrzi encoder smpte scambler anc_y/c ffrst ren wen oen 2 3 3 anc data insertion fifos trs insertion line number insertion crc insertion data_in [19:10] (luma) data_in [9:0] (chroma) blank trs_y/c det_trs 2 foen 10 w_clk 3 srst rstln hd-linx ? gs1501 hdtv serial digital formatter with anc fifos
gennum corporation 522 - 34 - 00 2 gs1501 absolute maximum ratings parameter value supply voltage -0.5v to +4.6v input voltage range (any input) -0.5v < v in < 5.5v operating temperature range 0 c t a 70 c storage temperature range -40 c t s 125 c lead temperature (soldering 10 seconds) 260 c dc electrical characteristics v dd = 3.0 to 3.6v, t a = 0 c to 70 c, unless otherwise shown parameter symbol conditions min typ max units notes positive supply voltage v dd 3.0 3.3 3.6 v supply current dd ? = 74.25mhz, t a = 25c - 402 480 ma input logic low voltage v il i leakage < 10a - - 0.8 v input logic high voltage v ih i leakage < 10a 2.1 3.3 5.0 v output logic low voltage v ol v dd = 3.0 to 3.6v, i ol = 4ma - 0.2 0.4 v output logic high voltage v oh v dd = 3.0 to 3.6v, i oh = -4ma 2.6 - - v ac electrical characteristics v dd =3.0 to 3.6v, t a = 0 c to 70 c parameter symbol conditions min typ max units notes clock input frequency f hsci - 74.25 80 mhz also supports 74.25/1.001mhz input data setup time t su 2.5 - - ns 50% levels input data hold time t ih 1.5 - - ns 50% levels input clock duty cycle 40 - 60 % output data hold time t oh with 15pf load 2.0 - - ns output enable time t oen with 15pf load - - 8 ns output disable time t odis with 15pf load - - 9 ns output data delay time t od with 15pf load - - 10 ns note 2 output data rise/fall time with 15pf load - - 2.5 ns 20% to 80% levels fifo input data setup time t fsu 8.0 - - ns note 1 fifo input data hold time t fih 4.0 - - ns note 1 notes: 1. the following signals need to adhere to this timing: anc_y/c , ren , wen , anc_in[9:0], ffrst. 2. timing of the ff_sta[2:0] outputs may be greater than specified.
gennum corporation 522 - 34 - 00 3 gs1501 pin connections v dd gnd oen tn nc nc nc nc nc nc nc nc nc v dd gnd f v h v dd gnd v dd gnd crc_ins ln_ins gnd trs_ins trs y/c srst bp_sc rstln code_protect gnd blank det_trs gnd v dd gnd pclk_in nc nc nc v dd gnd test nc nc ff_sta[0] ff_sta[1] ff_sta[2] anc_in[9] anc_in[8] v dd gnd anc_in[7] v dd gnd anc_in[6] anc_in[5] anc_in[4] anc_in[3] anc_in[2] anc_in[1] anc_in[0] v dd gnd w_clk v dd gnd foen ffrst wen ren v dd fm_i/e anc_y/c v dd data_out[19] data_out[18] data_out[17] data_out[16] data_out[15] v dd gnd data_out[14] data_out[13] data_out[12] data_out[11] data_out[10] data_out[9] v dd gnd data_out[8] data_out[7] v dd gnd data_out[6] data_out[5] data_out[4] data_out[3] data_out[2] data_out[1] data_out[0] data_in[19] data_in[18] data_in[17] data_in[16] data_in[15] data_in[14] v dd gnd data_in[13] data_in[12] data_in[11] data_in[10] v dd gnd data_in[9] data_in[8] data_in[7] data_in[6] data_in[5] data_in[4] data_in[3] data_in[2] data_in[1] data_in[0] v dd gnd 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 gs1501 top view
gennum corporation 522 - 34 - 00 4 gs1501 pin descriptions number symbol timing type description 1 pclk_in synchronous input parallel data clock input. 74.25mhz or 74.25/1.001mhz. 2, 4, 14, 19, 24, 37, 46, 50, 58, 69, 79, 82, 91, 94, 110, 116, 128 gnd n/a ground ground. ground power supply connections. 3, 20, 25, 38, 47, 51, 59, 68, 78, 81, 90, 93, 109, 115, 127 v dd n/a power power. positive power supply connections. 5 det_trs non- synchronous input control signal input. used to enable or disable the detection of the trs signals embedded in the video stream. when det _trs is high, the device detects the trs signals embedded in the input video stream and uses the detected hvf signals instead of the external hvf signals. when det _trs is low, trs detection is disabled. the device uses the external supplied hvf signals. 6blank synchronous wrt pclk_in input control signal input. when blank is low, the device sets the accompanying luma and chroma data to their appropriate blanking levels. when blank is high, the luma and chroma data streams pass through this stage of the device unaltered. see figure 3. 7, 17 gnd n/a this pin must be connected to gnd for normal operation 8 code_protect non- synchronous input control signal input. used to enable or disable re-mapping of out-of-range words contained in the active portion of the video signal. when this signal is high, the device re-maps out-of-range words contained within the active portion of the video signal into ccir-601 compliant words. values between 000-003 are re-mapped to 004. values between 3fc and 3ff are re-mapped to 3fb. when this signal is low, out-of-range words in the active video region pass through the device unaltered. 9 rstln synchronous wrt pclk_in input control signal input. this is the line number reset signal. a high-to-low edge of this signal resets the line number counter of the device to one (1). see figure 2. 10 bp_sc non- synchronous input control signal input. used to enable or bypass the smpte292m scrambler and nrz(i) encoder. when bp_sc is low, the video stream is scrambled according to smpte 292m and nrz(i) encoded. when bp_sc is high, the scrambler and nrz(i) encoder are by-passed. 11 srst non- synchronous input control signal input. used to reset the smpte292m scrambler and nrzi encoder. when srst is low, the scrambler and encoder operate normally. a low to high transition on srst causes the scrambler and encoder to reset. 12 trs_y/c non- synchronous input control signal input. only used when det_trs is high. when trs_y/c is high, the device detects and uses trs signals embedded in the luma (data_in[19:10]) channel. when trs_y/c is low, the device detects and uses trs signals embedded in the chroma (data_in[9:0]) channel. 13 trs_ins non- synchronous input control signal input. used to enable or disable insertion of trs into the video streams. when trs_ins is high, the device inserts smpte 292m compliant trs signals into the input luma and chroma data streams based on the supplied hvf signals. when trs_ins is low, the device does not insert trs signals.
gennum corporation 522 - 34 - 00 5 gs1501 15 ln_ins non- synchronous input control signal input. used to enable or disable insertion of line numbers into the video stream. when ln_ins is high, the device inserts smpte 292m compliant line number information into the luma and chroma channels. when ln_ins is low, the device does not insert the line number information into the luma and chroma channels. line number insertion is only available when user supplied external fvh data is used (det_trs set low). 16 crc_ins non- synchronous input control signal input. used to enable or disable insertion of crc's into the video stream. when crc_ins is high, the device calculates and inserts line based crcs. when crc_ins is low, this feature is disabled. 21 h synchronous wrt pclk_in input control signal input. this signal indicates the horizontal blanking period of the input video data stream. the device inserts hdtv trs based on the supplied hvf signals. refer to figure 4 for required timing of h relative to luma (data_in[19:10]) and chroma (data_in[9:0]). 22 v synchronous wrt pclk_in input control signal input. this signal indicates the vertical blanking period of the input video data streams. refer to figure 4 for required timing of v relative to luma (data_in[19:10]) and chroma (data_in[9:0]). 23 f synchronous wrt pclk_in input control signal input. this signal indicates the odd/even field of the input video data streams. refer to figure 4 for required timing of f relative to luma (data_in[19:10]) and chroma (data_in[9:0]). when the input video format is progressive scan, f should remain low at all times. 26, 27, 28, 29, 30, 31, 32, 33, 34, 65, 66, 67, 71, 72, nc n/a no connect. do not connect these pins 35 tn n/a test test pin. used for test purposes only. this pin must be connected to v dd for normal operation 36 oen see a/c electrical characteristics section input control signal input. used to enable data_out[19:0] output bus or set it to a high z state. when oen is low, the data_out[19:0] bus is enabled. when oen is high, the data_out[19:0] bus is disabled and in a high z state. 39, 40, 41, 42, 43, 44, 45, 48, 49, 52, 53, 54, 55, 56, 57, 60, 61, 62, 63, 64 data_out[19:0] synchronous wrt pclk_in outputs output data bus. the device generates a 20 bit wide data stream running at 74.25 (or 74.25/1.001) mhz. data_out[19] is the msb and data_out[0] is the lsb. 70 test n/a test te s t p i n . used for test purposes only. this pin must be connected to gnd for normal operation. pin descriptions (continued) number symbol timing type description
gennum corporation 522 - 34 - 00 6 gs1501 73, 74, 75 ff_sta[2:0] output control signal output. ff_sta[2:0] is the fifo status output to indicate the content level of the internal fifo. ff_sta[2:0]=000: error flag, fifo is under run. ff_sta[2:0]=001: fifo is empty. ff_sta[2:0]=010: fifo is almost empty (32 bytes filled). ff_sta[2:0]=011: fifo is ready. ff_sta[2:0]=100: fifo is half full. ff_sta[2:0]=101: fifo is almost full (992 bytes filled). ff_sta[2:0]=110: fifo is full. ff_sta[2:0]=111: error flag, fifo is over run. when anc_y/c is high, ff_sta indicates the status of the luma anc data buffer. when anc_y/c is low, it indicates the status of the chroma anc data buffer. see timing diagrams figures 5 to 14 and table 1. 76, 77, 80, 83, 84, 85, 86, 87, 88, 89 anc_in[9:0] synchronous wrt w_clk input anc data input bus. anc data to be inserted into the video stream is supplied via the anc_in[9:0] input data port. anc_in[9] is the msb (pin 76) and anc_in[0] is the lsb (pin 89). when fm_i/e =1, anc data intended to be placed into the current hanc region is written into the internal fifo during the time that the preceding active video region is passing through the device. the device begins inserting anc data stored in the fifo immediately after the line based crc words regardless of any other anc data that may be present in the stream (i.e. the device will over-write existing anc data in the data stream). 92 w_clk n/a input input clock. used to write information to the internal fifo. on the rising edge of w_clk, externally supplied anc data may be written into the internal luma or chroma fifo as determined by anc_y/c . 95 foen non- synchronous input control signal input. used to enable or disable the fifo status flags. when foen is low, the fifo status flags are enabled. when foen is high, the fifo status flags are disabled. 96 ffrst synchronous wrt pclk_in input control signal input. ffrst is used to supply synchronous reset signals to the fifo. when ffrst is low, the fifo is reset and all internal read and write address pointers are set to their starting locations. 97 wen synchronous wrt w_clk input control signal input. used to enable or disable writing to the internal fifo. when wen is high, writing to the internal fifo is not allowed. internal write address pointers are stopped at their current position. wen is sampled on the rising edge of w_clk. when wen is low, writing to the fifo is enabled. 98 ren synchronous wrt pclk_in input control signal input. used to enable or disable incrementation of the internal read address pointers. when ren is low, the internal read address pointers are incremented with each clock pulse. when ren is high, the internal read address pointers are stopped at their current position. pin descriptions (continued) number symbol timing type description
gennum corporation 522 - 34 - 00 7 gs1501 detailed description 1. data input and outputs data enters and exits the device synchronous to the rising edge of pclk_in as shown in figure 1. 2. input blanker data words entering the gs1501 can be dynamically set to luma and chroma blanking levels if desired as shown in figure 3. blanking is applied to both the luma and chroma channels simultaneously. 3. fifo the device does not flag transmission errors which might exist in the anc data packages. the internal fifo is 1024 words deep for each of luma and chroma channels. for those formats where the hanc region is greater than 1024 words, the user must take steps to ensure the fifo does not overflow, otherwise data may be lost. the gs1501 provides status signals to indicate the current content level of the internal fifo buffers, as described in section 3.1. 3.1 fifo status bits the device provides a status output signal ff_sta[2:0] that indicates the state of the current content level of the internal fifos. ff_sta[2:0] outputs 110, should the user supplied anc data have completely filled the internal fifo buffer. it is noted that once the internal fifo is full, any attempt to write data into the fifo will cause the fifo to overrun. the device flags this overrun state by setting ff_sta[2:0]=111. ff_sta[2:0] outputs 001, should all anc data in the fifo be extracted and inserted into the video stream and the internal fifo becomes empty. it is noted that once the internal fifo is empty, any attempt to read data from the fifo will cause the fifo to underrun. the device flags this underrun state by setting ff_sta[2:0]=000 and no data is inserted into the video stream. when anc_y/c is high, ff_sta indicates the status of the luma fifo buffer and when anc_y/c is low, ff_sta indicates the status of the chroma fifo buffer. it is important that the fifo status flags are as up-to-date as possible. therefore, certain fifo status flags are synchronized with respect to w_clk, and others are synchronized with respect to pclk_in. during a write cycle, status flags controlled by w_clk experience a three- cycle latency with respect to w_clk. during a read cycle, status flags controlled by pclk_in experience a three- cycle latency with respect to pclk_in. this information is summarized in table 1, and illustrated in figures 5 to 14. note: if a simultaneous fifo read and write operation is to be performed, the ff_sta[2:0] outputs should not be used as they may indicate incorrect fifo status. 100 fm_i/e non- synchronous input control signal input. when fm_i/e is high, the device operates in a mode where the fifo reset and read enable signals are generated internally. in this mode, the device limits the data insertion to the hanc region of the video stream. the anc data to be inserted into the current hanc region are externally supplied via the fifo interface during the active video period of the previous line using the wen signal. when fm_i/e is low, the device operates in another mode where the fifo reset and read enable signals are generated externally by the user and supplied to the device via the ffrst and ren control signal inputs. 101 anc_y/c synchronous wrt w_clk input control signal input. used to control insertion of anc data into the luma or chroma fifo. when anc_y/c is high, data written to the device is placed into the internal luma fifo, or read into the luma data stream. when anc_y/c is low, data written to the device is placed into the internal chroma fifo, or read into the chroma data stream. 103,104,105, 106, 107, 108, 111, 112, 113, 114 data_in [19:10] (luma channel) synchronous wrt pclk_in input input data bus. luma channel. data_in [19] is the msb of the luma input signal (pin 103). data_in [10] is the lsb of the luma input signal (pin 114). 117, 118, 119, 120, 121, 122, 123, 124, 125, 126 data_in [9:0] (chroma channel) synchronous wrt pclk_in input chroma input data bus. chroma channel data_in [9] is the msb of the chroma signal (pin 117). data_in [0] is the lsb of the chroma signal (pin 126). pin descriptions (continued) number symbol timing type description
gennum corporation 522 - 34 - 00 8 gs1501 3.2 fifo write control the fifo control signal wen is the write enable signal used to enable the loading of anc data into the internal fifo by the user through the fifo interface. note that the device only allows loading to one of the two internal fifo buffers through the fifo interface at a time. when anc_y/c is high, the luma fifo may be loaded. when anc_y/c is low, the chroma fifo may be loaded. when the internal fifo is not in the full or overrun states, it is ready to accept anc data. this should prompt the user to supply up to 1024 data words to the fifo by writing them through the fifo interface. upon seeing a rising edge on w_clk, the device will accept the word being presented on anc_in[9:0] into the selected fifo. each time w_clk is toggled, the internal write address pointer (luma or chroma) is incremented while wen is low. if wen is high, the write address pointer is not incremented and writing to the fifo is disabled. 3.3 fifo read control the fifo control signal ren is the read enable signal used to enable anc data insertion from the internal luma or chroma fifo buffer into its corresponding video stream, depending on the value of anc_y/c . the read address pointer increments with the internal clock at the video data rate while ren is low. if ren is high, the read address pointer will not increment. both address pointers for read and write can be reset to their starting positions by toggling the fifo reset signal ffrst from high to low. the device will insert the anc data into the video streams whenever data is present in the respective fifo buffer and the control signal ren is low. anc data will be extracted from the internal fifo buffer and inserted into the video stream until it is completely empty. when all words have been read from the fifo, the ff_sta[2:0] signal will be set to 001. 3.4 anc/data insertion in many cases, the user only wants to insert anc data into the hanc region. in order to make this frequently used mode easy, the device provides an automated insertion mode. when the control signal fm_i/e is high, the fifo control signals ffrst and ren cannot be used for the purpose described above. in this mode of operation, the device generates these reset and enable signals internally, which allows an automated insertion of anc data into the hanc region of the incoming luma or chroma data streams. the user still needs to supply a proper wen signal to enable the loading of anc data into the fifo. up to 1024 anc data words of each of the luma or chroma fifo(s) may be inserted during the hanc period. these data should be supplied into the fifo during the active video period. once all words have been read from the fifo, the ff_sta signal will be set to 001. 3.5 fifo external reset in external fifo control mode, the internal fifo address pointers are reset to zero (0) using ffrst . a recommended external reset process is shown in figure 15. table 1: fifo status indicator ff_sta[2:0] description synchronized to 000 error flag; fifo is under run pclk_in 001 fifo is empty pclk_in 010 fifo is almost empty; 32 bytes filled pclk_in 011 fifo is ready - 100 fifo is half full w_clk 101 fifo is almost full; 992 bytes filled w_clk 110 fifo is full w_clk 111 error flag; fifo is over run w_clk
gennum corporation 522 - 34 - 00 9 gs1501 fig. 1 synchronous i/o time fig. 2 rstln timing fig. 3 timing of dynamic data blanking fig. 4 hvf input timing data data pclk_in data_in data_out data data data data t su t ih t oh t od data pclk_in data_in[19:0] 000 3ff xyz (eav_id) ln 1 000 ln 0 eav for line#1 rstln line#1 inserted here n frames transistion from low to high can happen at any point pclk_in data_in[19:0] word x+3 word x+2 word x+1 word x word x+6 word x+8 word x+4 word x+7 data to be blanked blank pclk_in 3ff data_in[19:10] (luma) data_in[9:0] (chroma) 000 000 xyz (eav id) 3ff 000 000 xyz (eav id) 3ff 000 000 xyz (sav id) 3ff 000 000 xyz (sav id) yln 0 cln 0 h v f
gennum corporation 522 - 34 - 00 10 gs1501 fig. 5 fifo full to almost full read timing fig. 6 fifo almost full to half full read timing fig. 7 fifo half full to ready read timing pclk_in w_clk ren data_in[19:10] (luma) ff_sta[2:0] word1 word3 word2 word5 word4 word7 word6 word9 word8 word10 word11 9 cycles (will begin reading anc data out of the fifo and writing it into the luma stream at word1) 110 (full) 101 (almost full) word12 note that reference is made to the input data stream since the output is scrambled word13 word42 pclk_in w_clk ren data_in[19:10] (luma) ff_sta[2:0] word41 word44 word43 word46 word45 101 (almost full) 100 (half full) (low) word522 pclk_in w_clk ren data_in[19:10] (luma) ff_sta[2:0] word521 word524 word523 word526 word525 011 (ready) 100 (half full) (low)
gennum corporation 522 - 34 - 00 11 gs1501 fig. 8 fifo ready to almost empty read timing fig. 9 fifo almost empty to empty to read error timing fig. 10 fifo empty to almost empty write timing word999 pclk_in w_clk ren data_in[19:10] (luma) ff_sta[2:0] word998 word 1001 word 1000 word 1003 word 1002 010 (almost empty) 011 (ready) (low) pclk_in w_clk ren data_in[19:10] (luma) ff_sta[2:0] word 1032 010 (almost empty) 001 (empty) word 1035 word 1037 word 1038 word 1039 001 (empty) 000 (read error) word 1036 word 1033 word 1034 word 1031 word 1030 word 1029 word 1028 set high 9 cycles before point where reading data from fifo and writing it into the luma stream is to stop pclk_in w_clk anc_in[9:0] ff_sta[2:0] 001 (empty) word6 010 (almost empty) word5 wen word4 word3 word2 word1
gennum corporation 522 - 34 - 00 12 gs1501 fig. 11 fifo ready to half full write timing fig. 12 fifo ready to half full write timing fig. 13 fifo half full to almost full write timing pclk_in w_clk anc_in[9:0] ff_sta[2:0] word37 100 (half full) word36 word35 wen word34 word33 (low) 011 (ready) pclk_in w_clk anc_in[9:0] ff_sta[2:0] word513 100 (half full) word512 word511 wen word510 word509 (low) 011 (ready) pclk_in w_clk anc_in[9:0] ff_sta[2:0] word993 100 (half full) word992 word991 wen word990 word989 (low) 101 (almost full)
gennum corporation 522 - 34 - 00 13 gs1501 fig. 14 fifo almost full to full to write error timing fig. 15 recommended external fifo reset process pclk_in w_clk anc_in9:0] ff_sta[2:0] 101 (almost full) word 1024 word 1023 wen word 1022 word 1026 word 1028 110 (full) word 1025 111 (write error) 110 (full) word 1027 word 1029 pclk_in w_clk ffrst ren/wen at least 5 cycles of slowest clock high for at least 1 cycle after ffrst toggles
522 - 34 - 00 14 gennum corporation mailing address: p.o. box 489, stn. a, burlington, ontario, canada l7r 3y3 tel. +1 (905) 632-2996 fax. +1 (905) 632-5946 shipping address: 970 fraser drive, burlington, ontario, canada l7l 5p5 gennum japan corporation c-101, miyamae village, 2-10-42 miyamae, suginami-ku tokyo 168-0081, japan tel. +81 (03) 3334-7700 fax. +81 (03) 3247-8839 gennum uk limited 25 long garden walk, farnham, surrey, england gu9 7hx tel. +44 (0)1252 747 000 fax +44 (0)1252 726 523 gennum corporation assumes no responsibility for the use of any circuits described herein and makes no representations that th ey are free from patent infringement. ? copyright august 1999 gennum corporation. all rights reserved. printed in canada. gs1501 package dimensions 23.20 0.25 20.0 0.10 18.50 ref 17.20 0.25 14.0 0.10 12.50 ref 3.00 max 2.80 0.25 1.6 ref 0.30 max radius 0.13 min. radius 0.88 0.15 0.75 min 12 typ 0 - 7 0 -7 0.27 0.08 0.50 bsc 128 pin mqfp revision notes: updated absolute maximum ratings; updated ac and dc electrical characteristics tables; updated pin descriptions; added information to fifo section; corrected text in section 3.4, ? anc/data insertion ? ; updated figure 15. f o r l a t e s t p r o d uc t i n f o r m a t i on , v i s i t w w w . g ennu m . co m . caution electrostatic sensitive devices do not open packages or handle except at a static-free workstation document identification preliminary data sheet the product is in a preproduction phase and specifications are subject to change.

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